The present invention relates to an improvement in the word-line structure of a semiconductor memory, the improvement being particularly suited for use in dynamic random-access memories.
Increased bit capacities and densities in semiconductor memories have led to the following problem on the word lines that select memory cells. Since the word lines function as the gate electrodes of transistors in the memory cells, the word lines are fabricated from polysilicon, which has significant electrical resistivity. The resistivity can be reduced by mixing the polysilicon with a metal silicide such as tungsten silicide, but the resulting mixture, commonly referred to as polycide, still has significant resistivity, much greater than the resistivity of a metal such as aluminum. Because of this comparatively high resistivity, and because of the large number of transistors on each word line, the word lines present significant resistive (R) and capacitive (C) loads, and the attendant RC signal propagation delay slows the operation of the memory.
This problem has been attacked through three strategies in the prior art.
A first strategy places the driver circuit of each word line in the center of the word line, thus splitting the word line into two halves. Each half has only half the resistance and half the capacitance of the full word line, so the RC propagation delay is reduced by a factor of four. This strategy was used in memories with capacities measured in kilobits, but was inadequate for megabit memories.
A second strategy adds an aluminum shunt line, which has very low electrical resistance, above each polysilicon or polycide word line. The word line and shunt line are coupled at N+1 points, including the end points of the lines, by contact holes filled with interconnecting plugs of aluminum (N is an integer greater than one). This strategy reduces the RC delay by a factor of 4N.sup.2 , and has been used in one- and four-megabit memories.
In memories with higher integration densities, however, the second strategy encounters a further problem. To allow for mask alignment error in the fabrication process, the word lines and their aluminum shunt lines must be locally broadened at the points of contact with the aluminum interconnecting plugs. The consequent narrow spacing between adjacent lines at the interconnecting plugs makes fabrication difficult, and adversely affects production yields.
Memories with higher integration densities have, therefore, often adopted a third strategy. The third strategy divides the memory cell array into subarrays, so that each word line is divided into a corresponding plurality of shorter word lines, each shorter word line having its own driver. If a word line is divided into N such shorter word lines, the RC propagation delay is reduced by a factor of N.sup.2. The drivers themselves are activated via an aluminum word line which, although long, offers relatively little electrical resistance, has a comparatively small capacitive load, and thus causes little propagation delay.
A problem in this third strategy is that each word line requires N+1 drivers: one for the long aluminum line, and one for each shorter polysilicon or polycide line. The space taken up by the extra driving circuitry adds significantly to the length of the word lines, hence to the size of the memory device. Although a driver for a short polysilicon or polycide word line can use smaller transistors than are needed by a driver for long polysilicon or polycide word line, the size of the driver circuits does not scale down by a factor of N. To achieve a given reduction in propagation delay, the third strategy requires several times as much extra space as the second.